1. Field of the Invention
The present invention relates to a design technique of an LSI, and more particularly relates to a system and method for designing and manufacturing an LSI, and an electron beam (EB) data generating system for generating an EB data used in an electronic beam drawing apparatus.
2. Description of the Related Art
It is essential to use a computer for LSI design in order to reduce the time for design and check and remove an artificial mistake. A software program used for the LSI design is referred to as a CAD (Computer Aided Design) program. In the CAD program, a plurality of [Layout Layers (Digitized Layers)] are defined. A designer carries out the LSI design by arranging data of desirable pattern structures in the plurality of layout layers defined on the computer. In this way, a [Layout Data] indicating the pattern configuration of the designed LSI is obtained on the computer. Here, the pattern structure to be formed in a same physical layer is arranged in a same layout layer.
Also, in the foregoing LSI design, it is necessary to carry out the design for the LSI to meet [Design Rules]. The design rules defines a minimum pattern dimension and a minimum space dimension for each layout layer, and position relation between the layout layers in detail. It is necessary to obedience the design rules for the formation of a desirable device. A software program for checking whether or not the generated layout data meets the design rules is referred to as [DRC (Design Rule Checker)]. The designer modifies the layout data in accordance with an error data outputted by the DRC.
A reticle used in a lithography process is produced in accordance with the layout data generated in this way. In order to produce the reticle having a mask pattern determined based on the layout data, for example, [Electronic Beam (EB) Drawing Apparatus] is used. Here, it is necessary to convert the layout data into [EB Data] having a format suitable for the EB drawing apparatus (hereafter, referred to as [EB Data Converting Process]). For this reason, it is necessary to carry out a figure calculating process such as an inter-layer logic calculation, and a white/black inverting process.
In association with the higher integration and larger scale of the LSI, the number of layout patterns increases more and more. A large amount of time is required when all the layout patterns defined for the foregoing high integrated LSI are sequentially converted into the EB data. This causes a period for the design and development of the LSI to be made longer. For this reason, it is desired to provide the layout data suitable for the figure converting process.